high-speed cmos logic h ex inverting schmitt trigger the 74HC14 is useful to ?square up? slow input rise and fall times. due to the hysteresis voltage of the schmitt trigger, the 74HC14 finds applications in noisy environments. ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices 74HC14n / d 74HC14n dip 74HC14d so p t a = -55 to 125 c for all packages logic diagram pin 14 =v cc pin 7 = gnd pin assignment function table inputs output ay lh hl tiger electronic co.,ltd
74HC14 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +7.0 v v in dc input voltage (referenced to gnd) -1.5 to v cc +1.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types -55 +125 c t r , t f input rise and fall time (figure 1) - no limit* ns * when v in 50% v cc , i cc > 1ma this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
74HC14 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v 25 c to -55 c 85 c 125 c unit v t +max maximum positive- going input threshold voltage v out =0.1 v ? i out ? 20 a 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 v v t +min minimum positive- going input threshold voltage v out =0.1 v ? i out ? 20 a 2.0 4.5 6.0 1.0 2.3 3.0 0.95 2.25 2.95 0.95 2.25 2.95 v v t -max maximum negative- going input threshold voltage v out =v cc -0.1 v ? i out ? 20 a 2.0 4.5 6.0 0.9 2.0 2.6 0.95 2.05 2.65 0.95 2.05 2.65 v v t -min minimum negative- going input threshold voltage v out =v cc -0.1 v ? i out ? 20 a 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 v v h max note 1 maximum hysteresis voltage v out =0.1 v or v cc -0.1 v ? i out ? 20 a 2.0 4.5 6.0 1.2 2.25 3.0 1.2 2.25 3.0 1.2 2.25 3.0 v v h min note 1 minimum hysteresis voltage v out =0.1 v or v cc -0.1 v ? i out ? 20 a 2.0 4.5 6.5 0.2 0.4 0.5 0.2 0.4 0.5 0.2 0.4 0.5 v v oh minimum high-level output voltage v in v t -min ? i out ? 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in v t -min ? i out ? 4ma ? i out ? 5.2ma 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 v ol maximum low-level output voltage v in v t +max ? i out ? 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in v t +max ? i out ? 4ma ? i out ? 5.2ma 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 i in maximum input leakage current v in =v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in =v cc or gnd i out =0 a 6.0 1.0 10 40 a note: 1 v h min>(v t +min)-(v t -max); v h max=(v t +max)-(v t -min) .
74HC14 ac electrical characteristics (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed limit symbol parameter v 25 c to -55 c 85 c 125 c unit t plh , t phl maximum propagation delay, input a to output y (figures 1 and 2) 2.0 4.5 6.0 95 19 16 120 24 20 145 29 25 ns t tlh , t thl maximum output transition time, any output (figures 1 and 2) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns c in maximum input capacitance - 10 10 10 pf power dissipation capacitance (per inverter) typical @25 c,v cc =5.0 v c pd used to determine the no-load dynamic power consumption: p d =c pd v cc 2 f+i cc v cc 22 pf figure 1. switching waveforms figure 2. test circuit
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